libbsr0-devel
allocation services for the Barrier Synchronization Register on IBM POWER systems
The BSR is a hardware register which is memory mapped by processes which need very fast barrier synchronization. What it does is provide a set of counters which can be updated by different processors and have the updates propagate quickly to all the other processors. Using normal memory to do this requires the cache line with the counter to "bounce" between different processors in the system and every processor which needs to write to the memory must obtain ownership of the cache line and then cede it to the next processor which is doing an update. Each counter is only 1 byte and there are a limited number of the counters. The number of counters is what is referred to as the size of the register. Typically the BSR can also be partitioned into separate pieces which allow unrelated applications to use the resource in isolation. Authors: -------- Sonny Rao
LGPL v2.1 or later